1. Field of the Invention
This invention relates to reception of asynchronous tone signals as used in telecommunication systems and more particularly to a synchronizer circuit for use with tone reception equipment.
2. Description of the Prior Art
Most state of the art tone receivers employ as detectors peak detectors or rectifiers with filters, to drive two separate devices. Usually one of these devices is a parity checking circuit which in turn drives a parity timer, the second being an output circuit driven by both the detector outputs and the output of the parity timer. Such circuitry is taught in U.S. Pat. Nos. 2,719,959, 3,288,940 and U.S. Pat. No. 3,582,565.
In such tone receivers, the intended or usual operation requires that when a prescribed number of tone detectors (usually two) are activated, a parity checking circuit activates a parity timer. When the parity timer reaches its true or high state after a predetermined delay, the output circuitry is enabled so that it can latch up those output circuits being fed by detectors which have been turned on. The output circuits are then placed under the control of some other device such as a timer or handshake circuit, so that the output duration and/or identity is no longer controlled by the tone detectors.
The above-outlined arrangement creates problems in that the parity checking circuit and timer all have a finite out-of-time delay in their operation. As a result of this, a delay occurs in the activation of the output circuitry for some time after the parity timer should have enabled the outputs. If in the mean time an output has gone low or an extra one has gone high, the output circuits will latch into a state which represents a transient condition and not the condition which existed during the majority of the time that the parity timer was timing.
Because the parity timer is a long duration timer, its delay will be fairly large. In most applications, this has been on the order of several tens of microseconds for a timer with a timing period of around 25 milliseconds. In order to solve the resulting problem, one approach that has been attempted is to try to shorten the delay of the parity checking circuit and parity timer. This delay however can never be reduced to zero and will always leave some finite probability of the problem occurring. A more reasonable approach is to try to introduce a delay signal equal to the parity checking circuit delay plus the parity timer delay into the path between each detector and output circuit. The disadvantage of this approach is that delays could never be balanced exactly allowing a finite chance of error. Accordingly neither of these solutions is fully satisfactory and accordingly it is the object of the present invention to provide a new and improved approach to synchronization that overcomes such problems.